This invention relates to liquid crystal displays (LCDs) where a charge transfer scanning circuit is integrated into a LCD panel, and more particularly to a scanning line driving circuit for LCDs having discharging path for automatically discharging charges on scanning lines.
In general, a gate driver IC for scanning a LCD panel and a source driver IC for providing data to the LCD panel are respectively fabricated and then the driver ICs are packaged to the LCD panel. Because the conventional LCD packaging techniques fabricate driver ICs separately and package the driver ICs to the LCD panel, they have disadvantages in that the yield is reduced and the production cost rises.
To solve the problems occurred in case where driver ICs are separately fabricated and are packaged to a LCD panel, LCDs is which driver ICs are integrated into the LCD panel are proposed. FIG. 1 shows a LCD disclosed in Korean Patent Application No. 96-77694, in which a gate driver IC is integrated into a LCD panel. The gate driver-integrated LCD comprises a LCD panel 100, a gate driver IC 200 integrated into the LCD panel 100, a data driver IC 300 and a controller 500.
The LCD panel 100 comprises an upper glass substrate 110 where a color filter array is formed, a lower glass substrate 120 where a thin film transistor (TFT) array is formed, and LCs, not shown in FIG. 1, injected between the upper and lower glass substrates 110 and 120. Together with the TFT array, the gate driver IC 200 which drives scanning lines SL11 through SL1n of the LCD panel 100 is integrated in the lower glass substrate 120.
In the same manner as conventional LCDs, the data driver IC 300 is mounted on a tape carrier package(TCP) 400 and a pad part 310 of the data driver IC 300 is wire-bonded to the LCD panel 100. The controller 500 is for providing clock signals and data signals to the gate driver IC 200 integrated into the LCD panel 100 and the data driver IC 300. The controller 500 provides two-phase clock signals to the gate driver IC 300 through the LCD panel 100 and the data driver IC 300.
The gate driver IC 200 that is, the scanning line driving circuit is integrated into the portion of the lower glass substrate 120 which is not overlapped with the upper glass substrate 110 in an integrating TFT array. The detailed diagram of the scanning line driving circuit is shown in FIG. 2. The charge transfer type scanning line driving circuit 200 comprises a plurality of driving means 211-21n for driving scanning lines SL11-SL1n of the LCD panel 100, respectively.
The driving means 211-21n generate scanning line driving signals Vg_out1-Vg_outn to drive the scanning lines SL11-SL1n, respectively. Each of the driving means 211-21n comprises a first TFT T111-T11n for charge transfer, in which a clock signal Q1 or Q2 from the controller 500 is applied to a gate thereof, a capacitor C111-C11n for charge, which is connected to a source and the gate of the first TFT T111-T11n, and a second TFT T121-T12n for a buffer in which the source of the first TFT T111-T11n is connected to a gate thereof and which is driven by the first TFT T111-T11n to generate the scanning line driving signal Vg_out1-Vg_outn to the scanning line SL11-SL1n of the LCD panel 100.
In the plurality of driving means 211-21n, a predetermined voltage Vin of high level is applied to a drain of the first TFT T111 of the first driving means 211. A source of the first TFT of one of the plurality of driving means is connected to a drain of the first TFT of the following driving means. For example, the source of the first TFT T112 of the second driving means 212 is connected to the drain of the first TFT T113 of the third driving means 213. A gate voltage Vgh of the predetermined high level is applied to drains of the second TFTs T121-T12n.
The operation of the charge transfer type scanning line driving circuit will be described in detail below. Supposed that the first clock signal Q1 of two-phase clock signals Q1 and Q2 is turned on and the second clock signal Q2 is turned off. The first clock signal Q1 is applied to the first driving means 211. The first transistor T111 is tuned on by the first clock signal Q1 and the input voltage Vin of a predetermined high level is provided to the gate of the second transistor T121 through the first TFT T111. The second transistor T121 is turned on by the input voltage Vin. The gate voltage Vgh is provided to the first scanning line SL11 of the LCD panel 100 as the first scanning line driving signal Vg_out1 through the second TFT T121.
Subsequently, the first clock signal Q1 is turned off and the second clock signal Q2 is turned on. The second clock signal Q2 is provided to the second driving means 212 and charges charged to the capacitor C111 are applied to the drain of the first TFT T112 of the second driving means 212. The first TFT T112 of the second driving means 212 is turned on by the second clock signal and the charges charged in the capacitor C111 are provided to the gate of the second TFT T122 through the first transistor T112 and to the capacitor C112. The second transistor T122 is turned on. Accordingly, the gate voltage Vgh is provided through the second transistor T122 as the second scanning line driving signal Vg_out2 to the second scanning line SL12 of the LCD panel 100.
As above described, the first through the nth driving means 211-21n are driven to generate the first through the nth scanning line driving signals Vg_out1-Vg_outn in turn with repeated turning-on and turning-off of two clock signals Q1 and Q2. Therefore, the first through the nth scanning lines SL11-SL1n of the LCD panel 100 are driven in turn by the first through the nth scanning line driving signals Vg_out1-Vg_outn.
As compared with the conventional LCDs in which the driver ICs are fabricated and then packaged to the LCD panel, the LCD of FIG. 1 and FIG. 2 can improve yield and cost down by integrating the gate driver IC into the lower glass substrate together with the TFT array. However, because the scanning driving circuit of FIG. 2 has no discharge path, the charges charged to the scanning line can not be discharged, when the following scanning line driving signal is generated, following the generation of any one of the scanning line driving signals. For example, when the second scanning line driving signal Vg_out2 is generated to the second scanning line SL12, following the generation of the first scanning line driving signal Vg_out1 to the first scanning line SL11, charges charged to the first scanning line driving signal SL11 are not discharged. Accordingly, the second TFT T122 of the second driving means 212 is turned on and the second scanning line driving signal Vg_out2 is applied to the second scanning line SL12 while the first scanning line driving signal Vg_out1 is present in the first scanning line SL11, thereby resulting in deteriorating picture quality of LCD.